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| www.motorola.com/semiconductors m68hc05 microcontrollers mc68HC05P4A/d rev. 7, 5/2002 mc68HC05P4A te c h n i c a l d a t a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 te c h n i c a l d a t a motorola 3 mc68HC05P4A technical data to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digital dna is a trademark of motorola, inc. ? motorola, inc., 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68HC05P4A ? rev. 7.0 4 motorola revision history revision history date revision level description page number(s) may, 2002 7.0 corrected world wide web address and qualification status n/a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola list of sections 5 technical data ? mc68HC05P4A list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 17 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 27 section 3. central processor unit (cpu) . . . . . . . . . . . . 33 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 section 6. low-power modes. . . . . . . . . . . . . . . . . . . . . . 47 section 7. simple serial input/output port (siop) . . . . . 51 section 8. timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 section 9. computer operating properly (cop) . . . . . . 65 section 10. self-check mode . . . . . . . . . . . . . . . . . . . . . . 67 section 11. instruction set . . . . . . . . . . . . . . . . . . . . . . . . 69 section 12. electrical specifications . . . . . . . . . . . . . . . . 85 section 13. mechanical specifications . . . . . . . . . . . . . . 95 section 14. ordering information . . . . . . . . . . . . . . . . . . 97 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections technical data mc68HC05P4A ? rev. 7.0 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola table of contents 7 technical data ? mc68HC05P4A table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5 mcu structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.7 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.7.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.7.2 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.7.3 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.5 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.6 pa0 ? pa7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.7 sdo/pb5, sdi/pb6, and sck/pb7 . . . . . . . . . . . . . . . . . . .23 1.7.8 pc0 ? pc7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.7.9 pd5 and tcap/pd7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.8 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4 rom security feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC05P4A ? rev. 7.0 8 table of contents motorola section 3. central processor unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 index register (x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.1 h ? half carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.2 i ? interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5.3 n ? negative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.4 z ? zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5.5 c ? carry/borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.7 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . 38 4.4 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.6 optional external interrupts (pa0 ? pa7) . . . . . . . . . . . . . . . . . .42 4.7 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.5 computer operating properly (cop) reset . . . . . . . . . . . . . . . 46 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC05P4A ? rev. 7.0 technical data motorola table of contents 9 section 6. low-power modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.4 wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 section 7. simple serial input/output port (siop) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3 signal format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3.2 serial data out (sdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3.3 serial data in (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.4 siop registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 7.4.1 siop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4.2 siop status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.4.3 siop data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 section 8. timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.3 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.4 output compare register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.5 input capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.8 timer during wait or halt mode . . . . . . . . . . . . . . . . . . . . . . . . 64 8.9 timer during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC05P4A ? rev. 7.0 10 table of contents motorola section 9. computer operating properly (cop) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.3 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 9.4 cop during wait or halt mode. . . . . . . . . . . . . . . . . . . . . . . . .66 9.5 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 section 10. self-check mode 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 11. instruction set 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 11.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 11.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . 73 11.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 74 11.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . 76 11.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC05P4A ? rev. 7.0 technical data motorola table of contents 11 section 12. electrical specifications 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 12.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.6 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . . 88 12.7 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . . 89 12.8 5.0-volt siop timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.9 3.3-volt siop timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.10 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.11 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 section 13. mechanical specifications 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3 28-pin plastic dual in-line package (case 710-02) . . . . . . . . 95 13.4 28-pin small outline integrated circuit package (case 751f-04). . . . . . . . . . . . . . . . . . . . . . . . . . . 96 section 14. ordering information 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . . .98 14.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68HC05P4A ? rev. 7.0 12 table of contents motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola list of figures 13 technical data ? mc68HC05P4A list of figures figure title page 1-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1-2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1-3 port a pullup option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1-4 i/o circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2-2 i/o registers for the mc68HC05P4A . . . . . . . . . . . . . . . . . . . . 29 4-1 hardware interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4-2 irq function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5-1 power-on reset and reset . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6-1 stop/wait flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7-1 siop block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7-2 serial i/o port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7-3 siop control register (scr) . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7-4 siop status register (ssr). . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7-5 siop data register (sdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8-2 timer control register (tcr). . . . . . . . . . . . . . . . . . . . . . . . . . 62 8-3 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10-1 self-check circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12-1 siop timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12-2 stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68HC05P4A ? rev. 7.0 14 list of figures motorola figure title page 12-3 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12-4 power-on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12-5 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola list of tables 15 technical data ? mc68HC05P4A list of tables table title page 1-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4-1 vector address for interrupts and reset . . . . . . . . . . . . . . . . .38 10-1 self-check results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11-1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . . . 74 11-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . 75 11-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables technical data mc68HC05P4A ? rev. 7.0 16 list of tables motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola general description 17 technical data ? mc68HC05P4A section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5 mcu structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.7 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.7.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.7.2 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.7.3 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.5 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.6 pa0 ? pa7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7.7 sdo/pb5, sdi/pb6, and sck/pb7 . . . . . . . . . . . . . . . . . . .23 1.7.8 pc0 ? pc7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.7.9 pd5 and tcap/pd7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.8 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2 introduction the mc68HC05P4A is a 28-pin mcu (microcontroller unit) based on the mc68hc05p4. the memory map includes 4160 bytes of user rom and 176 bytes of ram. the mcu has two 8-bit input/output (i/o) ports, a and c. port b has three i/o pins and port d has two pins, one that is i/o and the other input only. the mc68HC05P4A includes a simple serial i/o peripheral (siop) and an on-chip mask programmable computer operating properly (cop) watchdog circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC05P4A ? rev. 7.0 18 general description motorola 1.3 features features of the mc68HC05P4A include: low cost hc05 core 28-pin package on-chip oscillator with rc (resistor capacitor) or crystal/ceramic resonator mask options 4160 bytes of user read-only memory (rom), including 16 user vector locations rom security feature (1) 176 bytes of on-chip random-access memory (ram) 16-bit timer 20 bidirectional input/output (i/o) lines, one input-only line mask programmable keyscan (pullups and interrupt) on eight port pins (pa0 ? pa7) two port pins with high current drive capability user mode self-check mode power-saving stop and wait modes edge-sensitive or edge- and level-sensitive interrupt trigger mask option simple serial i/o port mask option selectable computer operating properly (cop) watchdog timer 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the rom difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mask options mc68HC05P4A ? rev. 7.0 technical data motorola general description 19 1.4 mask options the mc68HC05P4A has 13 mask options: clock, rc or crystal irq , edge-sensitive only or edge- and level-sensitive siop, most significant bit (msb) or least significant bit (lsb) first cop watchdog timer, enable/disable keyscan pullups and interrupts on port a, enable/disable by pin stop instruction all mask options and the user rom are programmed on the 01 layer in fabrication. note: negative true signals like reset and irq will be denoted with an overline. 1.5 mcu structure figure 1-1 shows the structure of the mc68HC05P4A. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC05P4A ? rev. 7.0 20 general description motorola figure 1-1. block diagram sdo/pb5 sdi/pb6 sck/pb7 accumulator index register condition code register stack pointer program counter high program counter low cpu control alu cpu oscillator and divide by 3 2 data dir reg port b i/o lines internal processor clock reset irq osc1 osc2 timer system cop system 176 x 8 ram 240 x 8 self-check rom pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 data dir reg port a reg port a i/o lines pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 data dir reg port c reg port c i/o lines pd5 tcmp data dir reg port d reg port d i/o lines tcap/pd7 port b reg 4160 x 8 user rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68HC05P4A ? rev. 7.0 technical data motorola general description 21 1.6 pin assignments the mc68HC05P4A pin assignments are shown in figure 1-2 . figure 1-2. pin assignments 1.7 signal description the following paragraphs provide a description of the signals. 1.7.1 v dd and v ss power is supplied to the microcontroller through v dd and v ss . v dd is the power supply and v ss is ground. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 v dd osc1 osc2 tcap/pd7 tcmp pd5 pc0 pc1 reset irq pa7 pa5 pa4 pa3 pa2 pa1 pa0 pa6 15 16 17 18 19 20 sdo/pb5 sdi/pb6 sck/pb7 v ss 21 22 23 24 25 26 pc2 pc3 pc4 pc5 pc6 pc7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC05P4A ? rev. 7.0 22 general description motorola 1.7.2 irq this pin has a mask option that provides two different choices of interrupt triggering sensitivity. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to section 3. central processor unit (cpu) for more detail. 1.7.3 osc1 and osc2 these pins provide control input for an on-chip clock oscillator circuit. a crystal, a ceramic resonator, a resistor/capacitor combination, or an external signal connects to these pins and provides a system clock. a mask option selects either a crystal/ceramic resonator or a resistor/capacitor as the frequency determining element. the oscillator frequency is two times the internal bus rate. 1.7.4 reset this active low pin is used to reset the mcu to a known startup state by pulling reset low. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. 1.7.5 tcmp this pin provides an output for the output compare feature of the on-chip timer system. 1.7.6 pa0 ? pa7 port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $0000, and the data direction register is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a 1 to a data direction register (ddr) bit sets the corresponding port bit to output mode. port a has mask option enabled pullup devices and interrupt capability by pin. for a detailed description of i/o programming, refer to 1.8 input/output programming . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description signal description mc68HC05P4A ? rev. 7.0 technical data motorola general description 23 figure 1-3. port a pullup option 1.7.7 sdo/pb5, sdi/pb6, and sck/pb7 port b is a 3-bit bidirectional port. these pins are shared with the siop subsystem. refer to section 7. simple serial input/output port (siop) for a detailed description of the siop. the address of the port b data register is $0001, and the data direction register is at address $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bit to output mode. 1.7.8 pc0 ? pc7 port c is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the address of the port c data register is $0002, and the ddr is at address $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bit to output mode. two of the port c pins, pc0 and pc1, have a higher current drive capability. see section 12. electrical specifications . pa0 v dd v dd ddr bit normal port from all other port a pins irq schmitt trigger to interrupt logic mask option circuitry f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC05P4A ? rev. 7.0 24 general description motorola 1.7.9 pd5 and tcap/pd7 port d is a 2-bit port. pd5 is i/o and tcap/pd7 is input-only shared with the timer input capture. the address of the port d data register is $0003, and the data direction register is at address $0007. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bit to output mode. the tcap/pd7 pin controls the input capture feature for the on-chip programmable timer. this pin can be read at any time even if the tcap function is enabled. 1.8 input/output programming port pins may be programmed as inputs or outputs under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each i/o port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set to a logic 1. a pin is configured as an input if its corresponding ddr bit is cleared to a logic 0. at power-on or reset, all ddrs are cleared, which configures all pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. for further information, see table 1-1 and figure 1-4 . table 1-1. i/o pin functions r/w (1) 1. r/w is an internal signal. ddr i/o pin function 00 the i/o pin is in input mode. data is written into the output data latch. 01 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 11 the i/o pin is in an output mode. the output data latch is read. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description input/output programming mc68HC05P4A ? rev. 7.0 technical data motorola general description 25 figure 1-4. i/o circuitry data direction register bit latched output data bit i/o pin input reg bit input i/o output internal hc05 connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68HC05P4A ? rev. 7.0 26 general description motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola memory map 27 technical data ? mc68HC05P4A section 2. memory map 2.1 contents 2 . 2 i n t r o d u c t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2 . 3 r o m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2 . 4 r om s e curity f e at u r e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2 . 5 r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2.2 introduction the mc68HC05P4A has an 8-kbyte memory map, consisting of user read-only memory (rom), user random-access memory (ram), self-check rom, and input/output (i/o). see figure 2-1 and figure 2-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC05P4A ? rev. 7.0 28 memory map motorola $0000 i/o 32 bytes 0000 $0020 user rom (page zero) 48 bytes 0032 $0050 ram 176 bytes 0080 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map introduction mc68HC05P4A ? rev. 7.0 technical data motorola memory map 29 addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (porta) read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) read: pb7 pb6 pb5 00000 write: reset: unaffected by reset $0002 port c data register (portc) read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset $0003 port d data register (portd) read: pd7 0 pd5 10000 write: reset: unaffected by reset $0004 port a data direction (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 port b data direction (ddrb) read: ddrb7 ddrb6 ddrb5 11111 write: reset: 0 0 0 0 0 0 0 0 $0006 port c data direction (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $0007 port d data direction (ddrd) read: 0 0 ddrd5 00000 write: reset: 0 0 0 0 0 0 0 0 $0008 unimplemented $0009 unimplemented $000a siop control register (scr) read: 0 spe 0 mstr 0000 write: reset: 0 0 0 0 0 0 0 0 = unimplemented u = unaffected x = indeterminate figure 2-2. i/o registers for the mc68HC05P4A (sheet 1 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC05P4A ? rev. 7.0 30 memory map motorola $000b siop status register (ssr) read: spif dcol 0 0 0 0 0 0 write: reset: 0 0 0 0 0 0 0 0 $000c siop data register (sdr) read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $000d unimplemented $000e unimplemented $000f unimplemented $0010 unimplemented $0011 unimplemented $0012 timer control register (tcr) read: icie ocie toie 000 iedg olvl write: reset: 0 0 0 0 0 0 0 0 $0013 timer status register (tsr) read: icf ocf tof 0 0 0 0 0 write: reset: u u u 0 0 0 0 0 $0014 input capture msb (icrh) read: icrh7 icrh6 icrh5 icrh4 icrh3 icrh2 icrh1 icrh0 write: reset: unaffected by reset $0015 input capture lsb (icrl) read: icrl7 icrl6 icrl5 icrl4 icrl3 icrl2 icrl1 icrl0 write: reset: unaffected by reset $0016 output compare msb (ocrh) read: ocrh7 ocrh6 ocrh5 ocrh4 ocrh3 ocrh2 ocrh1 ocrh0 write: reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = unaffected x = indeterminate figure 2-2. i/o registers for the mc68HC05P4A (sheet 2 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map introduction mc68HC05P4A ? rev. 7.0 technical data motorola memory map 31 $0017 output compare lsb (ocrl) read: ocrl7 ocrl6 ocrl5 ocrl4 ocrl3 ocrl2 ocrl1 ocrl0 write: reset: unaffected by reset $0018 counter msb (crh) read: crh7 crh6 crh5 crh4 crh3 crh2 crh1 crh0 write: reset: unaffected by reset $0019 counter lsb (crl) read: crl7 crl6 crl5 crl4 crl3 crl2 crl1 crl0 write: reset: unaffected by reset $001a dual timer msb (dtmh) counter alternate register read: dtmh7 dtmh6 dtmh5 dtmh4 dtmh3 dtmh2 dtmh1 dtmh0 write: reset: unaffected by reset $001b dual timer lsb (dtml) counter alternate register read: dtml7 dtml6 dtml5 dtml4 dtml3 dtml2 dtml1 dtml0 write: reset: unaffected by reset $001c unimplemented $001d unimplemented $001e unimplemented $001f reserved r r r r r r r r addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = unaffected x = indeterminate figure 2-2. i/o registers for the mc68HC05P4A (sheet 3 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68HC05P4A ? rev. 7.0 32 memory map motorola 2.3 rom the user rom consists of 48 bytes of page zero rom from $0020 to $004f, 4096 bytes of rom from $0100 to $10ff, and 16 bytes of user vectors from $1ff0 to $1fff. the self-check rom and vectors are located from $1f00 to $1fef. 2.4 rom security feature a security feature (1) has been incorporated into the mc68HC05P4A to help prevent external reading of code in the rom. placing unique customer code at rom locations $0028 ? $002f aids in keeping customer developed software proprietary. 2.5 ram the user ram consists of 176 bytes of a shared stack area. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram in the range $00ff to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the rom difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola central processor unit (cpu) 33 technical data ? mc68HC05P4A section 3. central processor unit (cpu) 3.1 contents 3 . 2 i n t r o d u c t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3.3 a cc u m u l a t o r ( a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 . 4 i n d ex r e g i s t e r ( x ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 3.5 c o n d ition c o de r e g ister ( ccr) . . . . . . . . . . . . . . . . . . . . . . . . 3 4 3 . 5 . 1 h ? half c a rr y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 3 . 5 . 2 i ? i n terrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 3 . 5 . 3 n ? n e g a tiv e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 3 . 5 . 4 z ? zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 3 . 5 . 5 c ? ca r ry/b o rr o w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 3 . 6 s tack p o in t e r (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 3 . 7 p r o g r am c o u n t er ( p c ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 3.2 introduction this section describes the five cpu registers. cpu registers are not part of the memory map. 3.3 accumulator (a) the accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 70 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC05P4A ? rev. 7.0 34 central processor unit (cpu) motorola 3.4 index register (x) the index register is an 8-bit register used for the indexed addressing value to create an effective address. the index register also may be used as a temporary storage area. 3.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be tested individually by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. 3.5.1 h ? half carry this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. 3.5.2 i ? interrupt when this bit is set, timer and external interrupts are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. 3.5.3 n ? negative when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. 70 x ccr hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) stack pointer (sp) mc68HC05P4A ? rev. 7.0 technical data motorola central processor unit (cpu) 35 3.5.4 z ? zero when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0. 3.5.5 c ? carry/borrow when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 3.6 stack pointer (sp) the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the seven most significant bits (msb) are permanently set to 0000011. these seven bits are appended to the six least significant bits (lsb) to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 12 7 0 0000011 sp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68HC05P4A ? rev. 7.0 36 central processor unit (cpu) motorola 3.7 program counter (pc) the program counter is a 13-bit register that contains the address of the next byte to be fetched. note: the hc05 cpu core is capable of addressing a 64-kbyte memory map. for this implementation, however, the addressing registers are limited to an 8-kbyte memory map. 12 0 pc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola interrupts 37 technical data ? mc68HC05P4A section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . 38 4.4 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.6 optional external interrupts (pa0 ? pa7) . . . . . . . . . . . . . . . . . .42 4.7 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.2 introduction the mcu can be interrupted four different ways: two maskable hardware interrupts, irq and timer non-maskable software interrupt instruction (swi) optional external asynchronous interrupt on each port a pin (enabled by pullup mask option) interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. the return to interrupt (rti) instruction causes the register contents to be recovered from the stack and normal processing to resume. unlike reset , hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. note: the current instruction is the one already fetched and being operated on. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts technical data mc68HC05P4A ? rev. 7.0 38 interrupts motorola when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. table 4-1 lists vector addresses for all interrupts including reset. 4.3 hardware controlled interrupt sequence reset , stop, and wait are not interrupts in the strictest sense. however, they are acted upon in a similar manner. flowcharts for hardware interrupts are shown in figure 4-1 and for stop and wait in figure 6-1. sto p /w a i t flowchar t . a d i scu s s i o n i s p r ov i d e d h e r e. 1. reset ? a low input on the reset input pin causes the program to vector to its starting address, which is specified by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register also is set. much of the mcu is configured to a known state during this type of reset as described in section 5. resets . table 4-1. vector address for interrupts and reset register flag name interrupts cpu interrupt vector address n/a n/a reset reset $1ffe ? $1fff n/a n/a software swi $1ffc ? $1ffd n/a n/a external interrupt irq $1ffa ? $1ffb tsr icf timer input capture timer $1ff8 ? $1ff9 tsr ocf timer output capture timer $1ff8 ? $1ff9 tsr tof timer overflow timer $1ff8 ? $1ff9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts hardware controlled interrupt sequence mc68HC05P4A ? rev. 7.0 technical data motorola interrupts 39 figure 4-1. hardware interrupt flowchart from reset external interrupt irq internal interrupt timer i bit set is load pc from: irq : $1ffa ? $1ffb timer: $1ff8 ? $1ff9 set i bit stack pc, x, a, cc clear irq request latch complete interrupt routine and execute rti fetch next instruction execute instruction y y y n n n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts technical data mc68HC05P4A ? rev. 7.0 40 interrupts motorola 2. stop ? the stop instruction causes the oscillator to be turned off and the processor to "sleep" until an external interrupt (irq ) or reset occurs. 3. wait or halt ? the wait or halt instruction causes all processor clocks to stop, but leaves the timer clock running. this rest state of the processor can be cleared by reset, an external interrupt (irq ), or timer interrupt. these individual interrupts have no special wait vectors. see 6.4 wait instruction . 4.4 timer interrupt three different timer interrupt flags cause a timer interrupt when they are set and enabled. the interrupt flags are in the timer status register (tsr), and the enable bits are in the timer control register (tcr). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1ff8 and $1ff9. 4.5 external interrupt the irq pin drives an asynchronous interrupt to the cpu. an edge detector flip-flop is latched on the falling edge of irq . if either the output from the internal edge detector flip-flops or the level on the irq pin is low, a request is synchronized to the cpu to generate the irq interrupt. if the edge-sensitive only mask 0ption is selected, the output of the internal edge detector flip-flop is sampled and the input level on the irq pin is ignored. the interrupt service routine address is specified by the contents of memory locations $1ffa and $1ffb. a block diagram of the irq function is shown in figure 4-2 . note: the internal interrupt latch is cleared nine ph2 clock cycles after the interrupt is recognized (after location $1ffa is read). therefore, another external interrupt pulse can be latched during the irq service routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts external interrupt mc68HC05P4A ? rev. 7.0 technical data motorola interrupts 41 figure 4-2. irq function block diagram note: when the edge- and level-sensitive mask option is selected, the voltage applied to the irq pin must return to the high state before the rti instruction in the interrupt service routine is executed to avoid the processor re-entering the irq service routine. the irq pin is one source of an irq interrupt and a mask option can also enable the port a pins (pa0 ? pa7) to act as other irq interrupt sources. these sources are all combined into a single oring function to be latched by the irq latch. any enabled irq interrupt source sets the irq latch on the falling edge of the irq pin or a port a pin if port a interrupts have been enabled. if edge-only sensitivity is chosen by a mask option, only the irq latch output can activate a request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to: 1. falling edge on the irq pin with all enabled port a interrupt pins at a high level 2. falling edge on any enabled port a interrupt pin with all other enabled port a interrupt pins and the irq pin at a high level irq latch r v dd irq pin mask option (irq level) to irq processing in cpu to bih & bil instruction sensing rst irq vector fetch pa7 ddra7 pa0 ddra0 pa0 irq inhibit (mask option) pa7 irq inhibit (mask option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts technical data mc68HC05P4A ? rev. 7.0 42 interrupts motorola if level sensitivity is chosen, the active high state of the irq input can also activate an irq request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to: 1. low level on the irq pin 2. falling edge on the irq pin with all enabled port a interrupt pins at a high level 3. low level on any enabled port a interrupt pin 4. falling edge on any enabled port a interrupt pin with all enabled port a interrupt pins on the irq pin at a high level this interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1ffa and $1ffb. the irq latch is automatically cleared by entering the interrupt service routine. 4.6 optional external interrupts (pa0 ? pa7) the irq interrupt can be triggered by the inputs on the pa0 ? pa7 port pins if enabled by individual mask options. with pullup enabled, each port a pin can activate the irq interrupt function and the interrupt operation will be the same as for inputs to the irq pin. once enabled by mask option, each individual port a pin can be disabled as an interrupt source if its corresponding ddr bit is configured for output mode. note: the bih and bil instructions apply to the output of the logic or function of the enabled pa0?pa7 interrupt pins and the irq pin. the bih and bil instructions do not exclusively test the state of the irq pin. if enabled, the pa0?pa7 pins will cause an irq interrupt only if these individual pins are configured as inputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts software interrupt (swi) mc68HC05P4A ? rev. 7.0 technical data motorola interrupts 43 4.7 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt. it is executed regardless of the state of the i bit in the ccr. if the i bit is 0 (interrupts enabled), swi executes after interrupts which were pending when the swi was fetched but before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts technical data mc68HC05P4A ? rev. 7.0 44 interrupts motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola resets 45 technical data ? mc68HC05P4A section 5. resets 5.1 contents 5 . 2 i n t r o d u c t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 5 . 3 p o w e r- o n r e set ( p o r ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 5.4 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 5 . 5 c o m p u t e r o p e r a t i n g p r o p e r ly (c o p ) r e s e t . . . . . . . . . . . . . . . 4 6 5.2 introduction the mcu can be reset three ways: 1. initial power-on reset function 2. active low input to the reset pin 3. computer operating properly (cop) watchdog timer timeout 5.3 power-on reset (por) an internal reset is generated on power-up to allow the internal clock generator to stabilize. the power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay after the oscillator becomes active. if the reset pin is low at the end of this 4064-cycle delay, the mcu will remain in the reset condition until reset goes high. 5.4 reset pin the mcu is reset when a logic 0 is applied to the reset input for a period of one and one-half machine cycles (t cyc ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets technical data mc68HC05P4A ? rev. 7.0 46 resets motorola 5.5 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to time out, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop timeout was generated. the cop reset function is enabled or disabled by a mask option. refer to section 9. computer operating properly (cop) for more information on the cop. figure 5-1. power-on reset and reset osc1 2 reset internal clock 1 internal address bus 1 1ffe 1fff new new new op pch pcl v dd v dd threshold (1-2 v typical) t vddr t oxov 4064 t cyc t cyc t rl internal data bus 1 1ffe 1ffe 1ffe 1ffe new 1fff pch pcl op code code pcl pch notes: 1. internal timing signal and bus information are not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 3 pc pc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola low-power modes 47 technical data ? mc68HC05P4A section 6. low-power modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.4 wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2 introduction the mc68HC05P4A is capable of running in a low-power mode in each of its configurations. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the stop and wait instructions are not normally used if the computer operating properly (cop) watchdog timer is enabled. the flow of the stop and wait modes is shown in figure 6-1 . 6.3 stop mode execution of the stop instruction places the mcu in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including the cop watchdog timer. execution of the stop instruction automatically clears the i bit in the condition code register so that the irq external interrupt is enabled. all other registers and memory remain unaltered. all input/output lines remain unchanged. the mcu can be brought out of stop mode only by an irq external interrupt or an externally generated reset . when exiting the stop mode, the internal oscillator will resume after a 4064 ph2 clock cycle oscillator stabilization delay. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes technical data mc68HC05P4A ? rev. 7.0 48 low-power modes motorola 6.4 wait instruction the wait instruction places the mcu in a low-power mode, which consumes more power than stop mode. in wait mode, the ph2 clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated from the cop watchdog timer. execution of the wait instruction automatically clears the i bit in the condition code register enabling the irq external interrupt. all other registers, memory, and input/output lines remain in their previous state. if the 16-bit timer interrupt is enabled, it will cause the processor to exit wait mode and resume normal operation. the 16-bit timer may be used to generate a periodic exit from wait mode. the wait mode may also be exited when an irq external interrupt or reset occurs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes wait instruction mc68HC05P4A ? rev. 7.0 technical data motorola low-power modes 49 figure 6-1. stop/wait flowchart 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine wait stop to halt mask n external reset ? y n irq external interrupt? y n stop external oscillator, stop internal timer clock, reset startup delay restart external oscillator, restart stabilization delay stop internal processor clock, clear i-bit in ccr end of stabilization delay? y irq external interrupt? y n external oscillator active and internal timer clock active restart internal processor clock stop internal processor clock, clear i-bit in ccr timer internal interrupt? y n external reset ? y n stop cop internal reset? y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes technical data mc68HC05P4A ? rev. 7.0 50 low-power modes motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola simple serial input/output port (siop) 51 technical data ? mc68HC05P4A section 7. simple serial input/output port (siop) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3 signal format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3.2 serial data out (sdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3.3 serial data in (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.4 siop registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 7.4.1 siop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4.2 siop status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.4.3 siop data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.2 introduction this device includes a simple synchronous serial input/output (siop) port. the siop is a 3-wire master/slave system including serial clock (sck), serial data input (sdi), and serial data output (sdo). a mask programmable option determines whether the siop is most significant bit (msb) or least significant bit (lsb) first. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . simple serial input/output port (siop) technical data mc68HC05P4A ? rev. 7.0 52 simple serial input/output port (siop) motorola figure 7-1. siop block diagram 7.3 signal format the siop signal format is described here. 7.3.1 serial clock (sck) the state of sck between transmissions must be logic 1. the first falling edge of sck signals the beginning of a transmission. at this time, the first bit of received data is accepted at the sdi pin and the first bit of transmitted data is presented at the sdo pin. data is captured at the sdi pin on the rising edge of sck. subsequent falling edges shift the data and accept or present the next bit. the transmission is ended upon the eighth rising edge of sck. the maximum frequency of sck in slave mode is equal to e (bus clock) divided by four. that is, for a 4-mhz oscillator input, e becomes 2 mhz and the maximum sck frequency is 0.5 mhz. there is no minimum sck frequency. in master mode, the format is identical except that the sck pin is an output and the shift clock now originates internally. the master mode transmission frequency is fixed at e/4. 8-bit shift register d q r c reset sdo sck sdi msb/lsb mask option data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . simple serial input/output port (siop) signal format mc68HC05P4A ? rev. 7.0 technical data motorola simple serial input/output port (siop) 53 7.3.2 serial data out (sdo) a mask programmable option will be included to allow data to be transmitted in either msb first format or lsb first format. in either case, the state of the sdo pin always will reflect the value of the first bit received on the previous transmission if there was one. prior to enabling the siop, pb5 can be initialized to determine the beginning state if necessary. while the siop is enabled, pb5 can not be used as a standard output since that pin is coupled to the last stage of the serial shift register. on the first falling edge of sck, the first data bit to be shifted out is presented to the output pin. 7.3.3 serial data in (sdi) the sdi pin becomes an input as soon as the siop is enabled. new data may be presented to the sdi pin on the falling edge of sck. valid data must be present at least 100 ns before the rising edge of the clock and remain valid for 100 ns after the edge. figure 7-2. serial i/o port timing sdo bit 1 bit 2 bit 3 bit 7 sck bit 8 sdi bit 1 bit 2 bit 3 bit 7 bit 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . simple serial input/output port (siop) technical data mc68HC05P4A ? rev. 7.0 54 simple serial input/output port (siop) motorola 7.4 siop registers the siop registers are described here. 7.4.1 siop control register this register is located at address $000a and contains two bits. spe ? serial peripheral enable bit when set, this bit enables the serial i/o port and initializes the port b ddr such that pb5 (sdo) is output, pb6 (sdi) is input, and pb7 (sck) is input (slave mode only). the port b ddr can be altered subsequently as the application requires and the port b data register (except for pb5) can be manipulated as usual. however, these actions could affect the transmitted or received data. when spe is cleared, port b reverts to standard parallel i/o without affecting the port b data register or ddr. spe is readable and writable any time but clearing spe while a transmission is in progress will abort the transmission, reset the bit counter, and return port b to its normal i/o function. reset clears this bit. mstr ? master mode bit when set, this bit configures the siop for master mode. this means that the transmission is initiated by a write to the data register and the sck pin becomes an output providing a synchronous data clock at a fixed rate of e (bus clock) divided by four. while the device is in master mode, the sdo and sdi pins do not change function. these pins behave exactly as they would in slave mode. reset clears this bit address: $000a bit 7654321bit 0 read: 0 spe 0 mstr 0000 write: reset:00000000 = unimplemented figure 7-3. siop control register (scr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . simple serial input/output port (siop) siop registers mc68HC05P4A ? rev. 7.0 technical data motorola simple serial input/output port (siop) 55 and configures the siop for slave operation. mstr may be set at any time regardless of the state of spe. clearing mstr will abort any transmission in progress. 7.4.2 siop status register this register is located at address $000b and contains only two bits. spif ? serial peripheral interface flag bit this bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. it has no effect on any further transmissions and can be ignored without problem. spif is cleared by reading the ssr with spif set followed by a read or write of the serial data register. if it is cleared before the last edge of the next byte, it will be set again. reset clears this bit. dcol ? data collision bit this is a read-only status bit which indicates that an invalid access to the data register has been made. this can occur any time after the first falling edge of sck and before spif is set. a read or write of the data register during this time will result in invalid data being transmitted or received. note: dcol is cleared by reading the status register with spif set followed by a read or write of the data register. if the last part of the clearing sequence is done after another transmission has been started, dcol will be set again. if the dcol bit is set and the spif is not set, clearing the dcol requires turning the siop off then turning it back on. reset also clears this bit. address: $000b bit 7654321bit 0 read: spif dcol000000 write: reset:00000000 = unimplemented figure 7-4. siop status register (ssr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . simple serial input/output port (siop) technical data mc68HC05P4A ? rev. 7.0 56 simple serial input/output port (siop) motorola 7.4.3 siop data register this register is located at address $000c and is both the transmit and receive data register. this system is not double buffered and any write to this register will destroy the previous contents. the sdr can be read at any time, but if a transmission is in progress the results may be ambiguous. writes to the sdr while a transmission is in progress can cause invalid data to be transmitted and/or received. this register can be read and written only when the siop is enabled (spe = 1). address: $000c bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset figure 7-5. siop data register (sdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola timer 57 technical data ? mc68HC05P4A section 8. timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.3 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.4 output compare register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.5 input capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.8 timer during wait or halt mode . . . . . . . . . . . . . . . . . . . . . . . . 64 8.9 timer during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 8.2 introduction the timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. refer to figure 8-1 for a timer block diagram. each specific functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte also is accessed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer technical data mc68HC05P4A ? rev. 7.0 58 timer motorola note: the i bit in the ccr should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. figure 8-1. timer block diagram edge input (tcap) input capture register clock internal bus output compare register high byte low byte $16 $17 333 /4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status reg. icf ocf tof $13 icie iedg olvl output level reg. reset timer control reg. $12 output level (tcmp) interrupt circuit toie ocie d clk c q f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer counter mc68HC05P4A ? rev. 7.0 technical data motorola timer 59 8.3 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18 ? $19 (counter register) or $1a ? $1b (counter alternate register). a read from only the least significant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register first addresses the most significant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb also must be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. the free-running counter is configured to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator startup delay. because the free-running counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt can also be enabled when counter rollover occurs by setting its interrupt enable bit (toie). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer technical data mc68HC05P4A ? rev. 7.0 60 timer motorola 8.4 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the corresponding output compare flag (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare flag (ocf) is set or clear. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer input capture register mc68HC05P4A ? rev. 7.0 technical data motorola timer 61 8.5 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register ($14) msb, the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer technical data mc68HC05P4A ? rev. 7.0 62 timer motorola 8.6 timer control register the timer control register (tcr) is a read/write register containing five control bits. three bits control interrupts associated with the timer status register flags icf, ocf, and tof. icie ? input capture interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled ocie ? output compare interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled toie ? timer overflow interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled iedg ? input edge bit value of input edge determines which level transition on tcap pin will trigger free-running counter transfer to the input capture register. reset does not affect the iedg bit. 1 = positive edge 0 = negative edge olvl ? output level bit value of output level is clocked into output level register by the next successful output compare and will appear on the tcmp pin. 1 = high output 0 = low output address: $0012 bit 7654321bit 0 read: icie ocie toie 000 iedg olvl write: reset:00000000 = unimplemented figure 8-2. timer control register (tcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer timer status register mc68HC05P4A ? rev. 7.0 technical data motorola timer 63 bits 2, 3, and 4 ? not used always read 0 8.7 timer status register the timer status register (tsr) is a read-only register containing three status flag bits. icf ? input capture flag bit 1 = flag set when selected polarity edge is sensed by input capture edge detector 0 = flag cleared when tsr and input capture low register ($15) are accessed ocf ? output compare flag bit 1 = flag set when output compare register contents match the free-running counter contents 0 = flag cleared when tsr and output compare low register ($17) are accessed tof ? timer overflow flag bit 1 = flag set when free-running counter transition from $ffff to $0000 occurs 0 = flag cleared when tsr and counter low register ($19) are accessed bits 0 ? 4 ? not used always read 0 address: $0013 bit 7654321bit 0 read: icf ocf tof 00000 write: reset:uuu00000 = unimplemented figure 8-3. timer status register (tsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer technical data mc68HC05P4A ? rev. 7.0 64 timer motorola accessing the timer status register satisfies the first condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set, and 2. the lsb of the free-running counter is read but not for the purpose of servicing the flag. the counter alternate register at address $1a and $1b contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 8.8 timer during wait or halt mode the cpu clock halts during the wait or halt mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 8.9 timer during stop mode in stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer flags to wake up the mcu, but when the mcu does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. if reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola computer operating properly (cop) 65 technical data ? mc68HC05P4A section 9. computer operating properly (cop) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.3 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 9.4 cop during wait or halt mode. . . . . . . . . . . . . . . . . . . . . . . . .66 9.5 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2 introduction this device includes a watchdog computer operating properly (cop) feature as a mask option. the cop is implemented with an 18-bit ripple counter. this provides a timeout period of 64 milliseconds at a bus rate of 2 mhz. if the cop should time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset (por) or external reset. 9.3 resetting the cop preventing a cop reset is done by writing a 0 to the copr bit. this action will reset the counter and begin the timeout period again. the copr bit is bit 0 of address $1ff0. a read of address $1ff0 will access the user-defined rom data at that location. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68HC05P4A ? rev. 7.0 66 computer operating properly (cop) motorola 9.4 cop during wait or halt mode the cop will continue to operate normally during wait or halt mode. the software should pull the device out of wait or halt mode periodically and reset the cop by writing a logic 0 to the copr bit to prevent a cop reset. 9.5 cop during stop mode stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. the cop counter will be reset when stop mode is entered. if a reset is used to exit stop mode, the cop counter will be reset after the 4064 cycles of delay after stop mode. if an irq is used to exit stop mode, the cop counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. note: halt mode is not intended for normal use. this feature is provided to keep the cop watchdog timer active in the event a stop instruction is inadvertently executed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola self-check mode 67 technical data ? mc68HC05P4A section 10. self-check mode 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.2 introduction the self-check program resides at mask rom (read-only memory) locations $1f00 to $1fef. this program is designed to check the part ? s functionality with a minimum of support hardware. the computer operating properly (cop) subsystem is disabled in the self-check mode so that routines that feed the cop do not exist in the self-check program. 10.3 functional description the self-check mode is entered on the rising edge of reset if the irq pin is driven to double the supply voltage and the tcap/pd7 pin is at logic 1. reset must be held low for 4064 cycles after power-on reset (por) or for a time, t rl, for any other reset. after reset, the input/output (i/o), random-access memory (ram), rom, timer, simple serial input/output port (siop), and interrupts are tested. self-check results (using light-emitting diodes (leds) as monitors) are shown in table 10-1 . it is not recommended that the user code use any of the self-check code. the self-check code is subject to change at any time to improve testability or manufacturability. figure 10-1 illustrates a self-check circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . self-check mode technical data mc68HC05P4A ? rev. 7.0 68 self-check mode motorola figure 10-1. self-check circuit table 10-1. self-check results pc2 pc1 pc0 remarks 0 0 1 bad i/o 0 1 0 bad ram 0 1 1 bad timer 1 0 0 bad rom 1 0 1 bad serial 1 1 0 bad interrupt flashing good device all others bad device note: 0 indicates led is on; 1 indicates led is off. 10 k ? ? ? ? ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 69 technical data ? mc68HC05P4A section 11. instruction set 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 11.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 11.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . 73 11.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 74 11.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . 76 11.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2 introduction this section describes the m68HC05P4A addressing modes and instruction types. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 70 instruction set motorola 11.3 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes define the manner in which the cpu finds the data required to execute an instruction. the addressing modes are: 1. inherent 2. immediate 3. direct 4. extended 5. indexed, no offset 6. indexed, 8-bit offset 7. indexed, 16-bit offset 8. relative 11.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no memory address and are one byte long. 11.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set addressing modes mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 71 11.3.3 direct direct instructions can access any of the first 256 memory addresses with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are 3-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 11.3.4 extended extended instructions use only three bytes to access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 11.3.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000 ? $00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 11.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000 ? $01fe. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 72 instruction set motorola indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 11.3.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing the motorola assembler determines the shortest form of indexed addressing. 11.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two ? s complement byte that gives a branching range of ? 128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 73 11.4 instruction types the mcu instructions fall into five categories: 1. register/memory instructions 2. read-modify-write instructions 3. jump/branch instructions 4. bit manipulation instructions 5. control instructions 11.4.1 register/memory instructions most of these instructions use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 11-1 lists the register/memory instructions. table 11-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 74 instruction set motorola 11.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 11-2 lists the read-modify-write instructions. 11.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions table 11-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (one ? s complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (two ? s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 75 use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the conditional branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ? 128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 11-3 lists the jump and branch instructions. table 11-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 76 instruction set motorola 11.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the first 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. bit manipulation instructions use direct addressing. table 11-4 lists these instructions. 11.4.5 control instructions these register reference instructions control cpu operation during program execution. control instructions, listed in table 11-5 , use inherent addressing. table 11-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 11-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 77 11.5 instruction set summary table 11-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 11-6. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ?? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ?? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ????? rel 24 rr 3 bclr n opr clear bit n mn ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ????? rel 25 rr 3 beq rel branch if equal pc ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ????? rel 28 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 78 instruction set motorola bhcs rel branch if half-carry bit set pc ????? rel 29 rr 3 bhi rel branch if higher pc ????? rel 22 rr 3 bhs rel branch if higher or same pc ????? rel 24 rr 3 bih rel branch if irq pin high pc ????? rel 2f rr 3 bil rel branch if irq pin low pc ????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) ?? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ????? rel 25 rr 3 bls rel branch if lower or same pc ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc ????? rel 2c rr 3 bmi rel branch if minus pc ????? rel 2b rr 3 bms rel branch if interrupt mask set pc ????? rel 2d rr 3 bne rel branch if not equal pc ????? rel 26 rr 3 bpl rel branch if plus pc ????? rel 2a rr 3 bra rel branch always pc ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ????? rel 21 rr 3 brset n opr rel branch if bit n set pc ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 table 11-6. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 79 bsr rel branch to subroutine pc ? 1; push (pch) sp ? 1 pc ????? rel ad rr 6 clc clear carry bit c ???? 0inh98 2 cli clear interrupt mask i ? 0 ??? inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ?? 01 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ?? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one ? s complement) m ? (m) a ? (a) x ? (x) m ? (m) m ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ?? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? 1 a ? 1 x ? 1 m ? 1 m ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ?? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 table 11-6. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 80 instruction set motorola jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? 1 push (pch); sp ? 1 pc ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ?? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ?? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ?? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ??? 0inh42 1 1 neg opr nega negx neg opr ,x neg ,x negate byte (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ?? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 table 11-6. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 81 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ?? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ?? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ????? inh 9c 2 rti return from interrupt sp inh 80 9 rts return from subroutine sp ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (m) ? (c) ?? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ???? 1inh99 2 sei set interrupt mask i ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ?? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ??? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ?? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (m) ?? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 11-6. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 82 instruction set motorola 11.6 opcode map see table 11-7 . swi software interrupt pc ? 1; push (pch) sp ? 1; push (x) sp ? 1; push (a) sp ? 1; push (ccr) sp ? 1; i ? 1 ??? inh 83 1 0 tax transfer accumulator to index register x ????? inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ?? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 ??? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask ? ( ) negation (two ? s complement) ix1 indexed, 8-bit offset addressing mode set or cleared n any bit ? not affected table 11-6. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola instruction set 83 instruction set opcode map table 11-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 ta x 1inh 4 sta 2dir 5 sta 3ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set technical data mc68HC05P4A ? rev. 7.0 84 instruction set motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola electrical specifications 85 technical data ? mc68HC05P4A section 12. electrical specifications 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 12.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.6 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . . 88 12.7 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . . 89 12.8 5.0-volt siop timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.9 3.3-volt siop timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.10 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.11 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC05P4A ? rev. 7.0 86 electrical specifications motorola 12.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. keep v in and v out within the range v ss note: this device is not guaranteed to operate properly at the maximum ratings. refer to 12.6 5.0-volt dc electrical characteristics and 12.7 3.3-volt dc electrical characteristics for guaranteed operating conditions. rating symbol value unit supply voltage v dd ? 0.3 to + 7.0 v input voltage v in v ss ? 0.3 to v dd + 0.3 v self-check mode (irq pin only) v in v ss ? 0.3 to 2 x v dd +0.3 v current drain per pin excluding v dd and v ss i25ma storage temperature range t stg ? 65 to + 150 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications operating range mc68HC05P4A ? rev. 7.0 technical data motorola electrical specifications 87 12.4 operating range 12.5 thermal characteristics characteristic symbol value unit operating temperature range mc68HC05P4Ap (standard) mc68HC05P4Acp (extended) t a t l to t h 0 to +70 ? 40 to +85 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC05P4A ? rev. 7.0 88 electrical specifications motorola 12.6 5.0-volt dc electrical characteristics characteristic symbol min typ max unit output voltage i l oad = 10.0 ? 10.0 ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i l oad = ? 0.8 ma) pa0 ? pa 7 , p b 5 ? pb7, pc2 ? pc7, pd5 (i l oad = ? 5.0 ma) pc0 ? pc1 v oh v oh v dd ? 0.8 v dd ? 0.8 ? ? ? ? v output low voltage (i load = 1.6 ma) pa0 ? pa 7 , p b 5 ? pb7, pc2 ? pc7, pd5 (i load = 15 ma) pc0 ? pc1 v ol v ol ? ? ? ? 0.4 0.4 v input high voltage pa 0 ? pa 7 , p b 5 ? pb7, pc0 ? pc7, pd5, tcap/pd7, irq , reset , osc1 v ih 0.7 ? v dd v input low voltage pa 0 ? pa 7 , p b 5 ? pb7, pc0 ? pc7, pd5, tcap/pd7, irq , reset , osc1 v il v ss ? 0.2 ? 40 ? ? ? ? ? 3.5 1.5 5.0 8.0 20 5.0 3.0 8.0 15 30 ma ma ? pa 7 , p b 5 ? pb7, pc0 ? pc7, pd5 i oz ?? ?? ? ? ? ? 12 8 pf notes: 1.v dd = 5.0 vdc ? 40 ? 0.2 v 7.wait i dd is affected linearly by the osc2 capacitance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt dc electrical characteristics mc68HC05P4A ? rev. 7.0 technical data motorola electrical specifications 89 12.7 3.3-volt dc electrical characteristics characteristic symbol min typ max unit output voltage i l oad = 10.0 ? 10.0 ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i l oad = ? 0.2 ma) pa0 ? pa 7 , p b 5 ? pb7, pc2 ? pc7, pd5, tcmp (i l oad = ? 1.5 ma) pc0 ? pc1 v oh v oh v dd ? 0.3 v dd ? 0.3 ? ? ? ? v output low voltage (i l oad = 0.4 ma) pa0 ? pa 7 , p b 5 ? pb7, pc2 ? pc7, pd5, tcmp (i l oad = 6.0 ma) pc0 ? pc1 v ol v ol ? ? ? ? 0.3 0.3 v input high voltage pa 0 ? pa 7 , p b 5 ? pb7, pc0 ? pc7, pd5, tcap/pd7, irq , reset , osc1 v ih 0.7 ? v dd v input low voltage pa 0 ? pa 7 , p b 5 ? pb7, pc0 ? pc7, pd5, tcap/pd7, irq , reset , osc1 v il v ss ? 0.2 ? 40 ? ? ? ? ? 1.2 0.5 2.0 4.0 10 2.5 1.4 4.0 8.0 15 ma ma ? pa 7 , p b 5 ? pb7, pc0 ? pc7, pd5 i oz ?? ?? ? ? ? ? 12 8 pf notes: 1.v dd = 3.3 vdc ? 40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC05P4A ? rev. 7.0 90 electrical specifications motorola 12.8 5.0-volt siop timing 12.9 3.3-volt siop timing num. characteristic6 symbol min max unit operating frequency master slave f op(m) f op(s) 0.25 dc 0.25 0.25 f op 1 cycle time master slave t cyc(m) t cyc(s) 4.0 ? 4.0 4.0 t cyc 2 clock (sck) low time t cyc 932 ? ns 3 sdo data valid time t v ? 200 ns 4 sdo hold time t ho 0 ? ns 5 sdi setup time t s 100 ? ns 6 sdi hold time t h 100 ? ns notes: 1. v dd = 5.0 vdc ? 40 ? 4.0 4.0 t cyc 2 clock (sck) low time t cyc 1980 ? ns 3 sdo data valid time t v ? 400 ns 4 sdo hold time t ho 0 ? ns 5 sdi setup time t s 200 ? ns 6 sdi hold time t h 200 ? ns notes: 1. v dd = 3.3 vdc ? 40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0-volt control timing mc68HC05P4A ? rev. 7.0 technical data motorola electrical specifications 91 figure 12-1. siop timing diagram 12.10 5.0-volt control timing sdo bit 0 bit 1 bit 6 sck bit 7 sdi bit 0 bit 1 bit 6 bit 7 1 2 3 4 5 6 characteristic symbol min max unit frequency of operation crystal option external clock option f osc ? dc 4.2 4.2 mhz internal operating frequency crystal (f osc ? dc 2.1 2.1 mhz cycle time t cyc 480 ? ns crystal oscillator startup time t oxov ? 100 ms stop recovery startup time (crystal oscillator) t ilch ? 100 ms reset pulse width t rl 1.5 ? t cyc interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil * ? t cyc osc1 pulse width t oh, t ol 90 ? ns note: 1. v dd = 5.0 vdc ? 40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC05P4A ? rev. 7.0 92 electrical specifications motorola 12.11 3.3-volt control timing characteristic symbol min max unit frequency of operation crystal option external clock option f osc ? dc 2.0 2.0 mhz internal operating frequency crystal (f osc ? dc 1.0 1.0 mhz cycle time t cyc 1000 ? ns crystal oscillator startup time t oxov ? 100 ms stop recovery startup time (crystal oscillator) t ilch ? 100 ms reset pulse width, excluding powerup t rl 1.5 ? t cyc interrupt pulse width low (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil * ? t cyc osc1 pulse width t oh, t ol 200 ? ns notes: 1. v dd = 3.3 vdc ? 40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt control timing mc68HC05P4A ? rev. 7.0 technical data motorola electrical specifications 93 figure 12-2. stop recovery timing figure 12-3. external interrupt timing 1fff 1ffe 1ffe 1ffe 1ffe 1ffe 4 reset or interrupt vector fetch internal clock irq 3 osc 1 irq 2 internal address bus reset notes: 1. represents the internal clocking of the osc1 pin. 2. irq pin edge-sensitive mask option 3. irq pin level- and edge-sensitive mask option 4. reset vector address shown for timing example t rl t ilih 4064 t cyc ? ilih t ilil t ilih t irq (pin) irq n irq 1 rq (mcu) normally used with wire-ored connection edge-sensitive trigger condition the minimum pulse width (t ilih ) is either 125 ns (v dd = 5 v) or 250 ns (v dd = 3 v). the period t ilil should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 19 t cyc cycles. level-sensitive trigger condition if after servicing an interrupt the irq remains low, then the next interrupt is recognized. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68HC05P4A ? rev. 7.0 94 electrical specifications motorola figure 12-4. power-on reset timing figure 12-5. external reset timing sc1 pin v dd 4064 t cyc in t e rn al clock in t e rn al address bus in t e rn al data bus 1fff 1ffe 1ffe 1ffe 1ffe new pcl new pch 1ffe 1ffe v dd th re sh ol d (ty pi c al ly 1 -2 v ) t vddr notes: 1. internal clock, internal address bus, and internal data bus signals are not available externally. 2. an internal por reset is triggered as v dd rises through a threshold (typically 1 ? 2 v). nternal clock nternal ddress bus reset t rl new pc dummy nternal data bus new pc op code 1fff new pcl 1ffe new pch 1ffe 1ffe 1ffe notes: 1. internal clock, internal address bus, and internal data bus signals are not available externally. 2. the next rising edge of the internal processor clock after the rising edge of reset initiates the reset sequence. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola mechanical specifications 95 technical data ? mc68HC05P4A section 13. mechanical specifications 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3 28-pin plastic dual in-line package (case 710-02) . . . . . . . . 95 13.4 28-pin small outline integrated circuit package (case 751f-04). . . . . . . . . . . . . . . . . . . . . . . . . . . 96 13.2 introduction this section describes the dimensions of the dual in-line package (dip) and small outline integrated circuit (soic) mcu package. 13.3 28-pin plastic dual in-line package (case 710-02) !"!#! ! $ ! ! ! # ! 114 15 28 b a c n k m j d f hg l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data mc68HC05P4A ? rev. 7.0 96 mechanical specifications motorola 13.4 28-pin small outline integrated circuit package (case 751f-04) !$ $ % ! $ ! !! ! # ! # !"!#! ! # ! # ! # ! # " ! !"!#! ! -a- -b- 114 15 28 -t- c ! ! m j -t- k 26x g 28x d 14x p r x 45 ! f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC05P4A ? rev. 7.0 technical data motorola ordering information 97 technical data ? mc68HC05P4A section 14. ordering information 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . . .98 14.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 100 14.2 introduction this section contains instructions for ordering custom-masked rom mcus. 14.3 mcu ordering forms to initiate an order for a rom-based mcu, first obtain the current ordering form for the mcu from a motorola representative. submit the following items when ordering mcus: a current mcu ordering form that is completely filled out (contact your motorola sales office for assistance.) a copy of the customer specification if the customer specification deviates from the motorola specification for the mcu customer ? s application program on one of the media listed in 14.4 application program media f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information technical data mc68HC05P4A ? rev. 7.0 98 ordering information motorola 14.4 application program media deliver the application program to motorola in one of the following media: macintosh ? ms-dos ? ms-dos ? customer name customer part number project or product name file name of object code date name of operating system that formatted diskette formatted capacity of diskette on diskettes, the application program must be in motorola ? s s-record format (s1 and s9 records), a character-based object file format generated by m6805 cross assemblers and linkers. note: begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom locations or leave all non-user rom locations blank. refer to the current 1. macintosh is a registered trademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of international business machines corporation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information rom program verification mc68HC05P4A ? rev. 7.0 technical data motorola ordering information 99 mcu ordering form for additional requirements. motorola may request pattern re-submission if non-user areas contain any non-zero code. if the memory map has two user rom areas with the same address, then write the two areas in separate files on the diskette. label the diskette with both file names. in addition to the object code, a file containing the source code can be included. motorola keeps this code private and uses it only to expedite rom pattern generation in case of any difficulty with the object code. label the diskette with the file name of the source code. 14.5 rom program verification the primary use for the on-chip rom is to hold the customer ? s application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. motorola inputs the customer ? s application program code into a computer program that generates a listing verify file. the listing verify file represents the memory map of the mcu. the listing verify file contains the user rom code and may also contain non-user rom code, such as self-check code. motorola sends the customer a computer printout of the listing verify file along with a listing verify form. to aid the customer in checking the listing verify file, motorola will program the listing verify file into customer-supplied blank preformatted macintosh or dos disks. all original pattern media are filed for contractual purposes and are not returned. check the listing verify file thoroughly, then complete and sign the listing verify form, and return the listing verify form to motorola. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information technical data mc68HC05P4A ? rev. 7.0 100 ordering information motorola 14.6 rom verification units (rvus) after receiving the signed listing verify form, motorola manufactures a custom photographic mask. the mask contains the customer ? s application program and is used to process silicon wafers. the application program cannot be changed after the manufacture of the mask begins. motorola then produces 10 mcus, called rvus, and sends the rvus to the customer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customer ? s user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for qualification or production. rvus are not guaranteed by motorola quality assurance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? ty p i c a l s ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 mc68HC05P4A/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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